Memory access method and semiconductor memory device

Abstract

A semiconductor memory device includes a memory cell array provided with blocks each having a plurality of memory cells arranged in columns and rows, a column selection circuit selecting a column via bit lines based on a column section signal, a word line driver circuit selecting a row via a word line based on a row selection signal and the column selection signal, and a write/read circuit writing data to and reading data from a selected memory cell via the bit lines based on a write and read switching signal. The selected memory cell is arranged at a position determined by the column selected by the column selection circuit and the row selected by the word line driver circuit within one block. Rows corresponding to the blocks are provided in common with the same number of word lines as the columns, and the memory cells arranged in one row within one block are coupled to mutually different word lines.