The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 13, 2012
Filed:
Jan. 29, 2009
James Karp, Saratoga, CA (US);
Richard C. LI, Cupertino, CA (US);
Fu-hing Ho, San Francisco, CA (US);
Mohammed Fakhruddin, Campbell, CA (US);
James Karp, Saratoga, CA (US);
Richard C. Li, Cupertino, CA (US);
Fu-Hing Ho, San Francisco, CA (US);
Mohammed Fakhruddin, Campbell, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
An input/output ('I/O') circuit has a first N-channel metal-oxide semiconductor ('NMOS') field-effect transistor (“FET”) coupled to the input pin with a silicide block. A first P-channel metal-oxide semiconductor (“PMOS”) FET is directly connected to the input pin, with its N-well electrically coupled to an ESD well bias circuit. An NMOS low-voltage differential signal (“LVDS”) driver is also directly connected to the input pin, and has cascaded NMOS FETs. The first NMOS FET of the LVDS driver is fabricated within a first P-tap guard ring electrically coupled to ground and an N-well guard ring coupled to the ESD well bias. The second NMOS FET of the LVDS driver is fabricated within a second P-tap guard ring electrically coupled to ground.