The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 13, 2012
Filed:
May. 16, 2008
Bart Van Schravendijk, Sunnyvale, CA (US);
Richard S. Hill, Atherton, CA (US);
Wilbert Van Den Hoek, Saratoga, CA (US);
Harald Te Nijenhuis, San Jose, CA (US);
Bart van Schravendijk, Sunnyvale, CA (US);
Richard S. Hill, Atherton, CA (US);
Wilbert van den Hoek, Saratoga, CA (US);
Harald te Nijenhuis, San Jose, CA (US);
Novellus Systems, Inc., San Jose, CA (US);
Abstract
In-situ semiconductor process that can fill high aspect ratio (typically at least 6:1, for example 7:1 or higher), narrow width (typically sub 0.13 micron, for example 0.1 micron or less) gaps without damaging underlying features and little or no incidence of voids or weak spots is provided. A protective layer is deposited to protect underlying features in regions of the substrate having lower feature density so that unwanted material may be removed from regions of the substrate having higher feature density. This protective layer may deposits thicker on a low density feature than on a high density feature and may be deposited using a PECVD process or low sputter/deposition ratio HDP CVD process. This protective layer may also be a metallic oxide layer that is resistant to fluorine etching, such as zirconium oxide (ZrO) or aluminum oxide (AlO).