The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 13, 2012

Filed:

Oct. 19, 2009
Applicants:

Dew-ill Chung, Suwon-si, KR;

Han-soo Kim, Suwon-si, KR;

Jae-hun Jeong, Hwaseong-si, KR;

Jin-soo Lim, Seoul, KR;

Ki-hyun Kim, Hwaseong-si, KR;

Ju-young Lim, Seoul, KR;

Inventors:

Dew-ill Chung, Suwon-si, KR;

Han-soo Kim, Suwon-si, KR;

Jae-hun Jeong, Hwaseong-si, KR;

Jin-soo Lim, Seoul, KR;

Ki-hyun Kim, Hwaseong-si, KR;

Ju-young Lim, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 21/336 (2006.01); H01L 21/8236 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of fabricating a non-volatile memory device according to an example embodiment may include etching a plurality of sacrificial films and insulation films to form a plurality of first openings that expose a plurality of first portions of a semiconductor substrate. A plurality of channel layers may be formed in the plurality of first openings so as to coat the plurality of first portions of the semiconductor substrate and side surfaces of the plurality of first openings. A plurality of insulation pillars may be formed on the plurality of channel layers so as to fill the plurality of first openings. The plurality of sacrificial films and insulation films may be further etched to form a plurality of second openings that expose a plurality of second portions of the semiconductor substrate. A plurality of side openings may be formed by removing the plurality of sacrificial films. A plurality of gate dielectric films may be formed on surfaces of the plurality of side openings. A plurality of gate electrodes may be formed on the plurality of gate dielectric films so as to fill the plurality of side openings.


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