The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 06, 2012
Filed:
Nov. 08, 2007
Serafino Bueti, Waterbury, VT (US);
Kenneth J. Goodnow, Essex Junction, VT (US);
Todd E. Leonard, Williston, VT (US);
Gregory J. Mann, Winfield, IL (US);
Peter A. Sandon, Essex Junction, VT (US);
Peter A. Twombly, Shelburne, VT (US);
Charles S. Woodruff, Charlotte, VT (US);
Serafino Bueti, Waterbury, VT (US);
Kenneth J. Goodnow, Essex Junction, VT (US);
Todd E. Leonard, Williston, VT (US);
Gregory J. Mann, Winfield, IL (US);
Peter A. Sandon, Essex Junction, VT (US);
Peter A. Twombly, Shelburne, VT (US);
Charles S. Woodruff, Charlotte, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Method for correcting timing failures in an integrated circuit and device for monitoring an integrated circuit. The method includes placing a first and second latch near a critical path. The first latch has an input comprising a data value on the critical path. The method further includes generating a delayed data value from the data value, latching the delayed data value in the second latch, comparing the data value with the delayed data value to determine whether the critical path comprises a timing failure condition, and executing a predetermined corrective measure for the critical path. The invention is also directed to a design structure on which a circuit resides.