The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 06, 2012
Filed:
Apr. 13, 2009
Richard W. Doing, Raleigh, NC (US);
Susan E. Eisen, Round Rock, TX (US);
David S. Levitan, Austin, TX (US);
Kevin N. Magill, Raleigh, NC (US);
Brian R. Mestan, Austin, TX (US);
Balaram Sinharoy, Poughkeepsie, NY (US);
Benjamin W. Stolt, Austin, TX (US);
Jeffrey R. Summers, Raleigh, NC (US);
Albert J. Van Norstrand, Jr., Round Rock, TX (US);
Richard W. Doing, Raleigh, NC (US);
Susan E. Eisen, Round Rock, TX (US);
David S. Levitan, Austin, TX (US);
Kevin N. Magill, Raleigh, NC (US);
Brian R. Mestan, Austin, TX (US);
Balaram Sinharoy, Poughkeepsie, NY (US);
Benjamin W. Stolt, Austin, TX (US);
Jeffrey R. Summers, Raleigh, NC (US);
Albert J. Van Norstrand, Jr., Round Rock, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Mechanisms, in a data processing system, are provided for tracking effective addresses through a processor pipeline of the data processing system. The mechanisms comprise logic for fetching an instruction from an instruction cache and associating, by an effective address table logic in the data processing system, an entry in an effective address table (EAT) data structure with the fetched instruction. The mechanisms further comprise logic for associating an effective address tag (eatag) with the fetched instruction, the eatag comprising a base eatag that points to the entry in the EAT and an eatag offset. Moreover, the mechanisms comprise logic for processing the instruction through the processor pipeline by processing the eatag.