The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 06, 2012
Filed:
Jun. 19, 2003
Laurence B. Boucher, Saratoga, CA (US);
Stephen E. J. Blightman, San Jose, CA (US);
Peter K. Craft, San Francisco, CA (US);
David A. Higgen, Saratoga, CA (US);
Clive M. Philbrick, San Jose, CA (US);
Daryl D. Starr, Milpitas, CA (US);
Laurence B. Boucher, Saratoga, CA (US);
Stephen E. J. Blightman, San Jose, CA (US);
Peter K. Craft, San Francisco, CA (US);
David A. Higgen, Saratoga, CA (US);
Clive M. Philbrick, San Jose, CA (US);
Daryl D. Starr, Milpitas, CA (US);
Alacritech, Inc., San Jose, CA (US);
Abstract
An intelligent network interface card (INIC) or communication processing device (CPD) works with a host computer for data communication. The device provides a fast-path that avoids protocol processing for most messages, greatly accelerating data transfer and offloading time-intensive processing tasks from the host CPU. The host retains a fallback processing capability for messages that do not fit fast-path criteria, with the device providing assistance such as validation even for slow-path messages, and messages being selected for either fast-path or slow-path processing. A context for a connection is defined that allows the device to move data, free of headers, directly to or from a destination or source in the host. The context can be passed back to the host for message processing by the host. The device contains specialized hardware circuits that are much faster at their specific tasks than a general purpose CPU. A preferred embodiment includes a trio of pipelined processors devoted to transmit, receive and utility processing, providing full duplex communication for four Fast Ethernet nodes.