The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 06, 2012

Filed:

Jun. 24, 2009
Applicants:

Bert H. Tanaka, Saratoga, CA (US);

Daniel J. Maltbie, Santa Cruz, CA (US);

Joseph R. Mihelich, Fremont, CA (US);

Inventors:

Bert H. Tanaka, Saratoga, CA (US);

Daniel J. Maltbie, Santa Cruz, CA (US);

Joseph R. Mihelich, Fremont, CA (US);

Assignee:

Fortinet, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 12/26 (2006.01);
U.S. Cl.
CPC ...
Abstract

A mechanism is disclosed for enabling load balancing to be achieved in a loop-free switching path, reverse path learning network, such as an Ethernet network. The network is divided into a plurality of virtual networks, with each virtual network providing a different path through the network. When it comes time to send a set of information through the network, one of the plurality of virtual networks, and hence, one of the plurality of paths, is selected. The set of information is then updated to indicate the selected virtual network, and sent into the network to be transported along the selected path. With multiple paths, and with the ability to select between the multiple paths, it is possible to balance the load imposed on the multiple paths.


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