The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 06, 2012
Filed:
Jan. 22, 2007
Andrew Walker, Mountain View, CA (US);
Helmut Puchner, Santa Clara, CA (US);
Andrew Walker, Mountain View, CA (US);
Helmut Puchner, Santa Clara, CA (US);
Cypress Semiconductor Corporation, San Jose, CA (US);
Abstract
A protection circuit and method are provided for protecting semiconductor devices from electrostatic discharge (ESD). Generally, the ESD protection circuit includes a silicon controlled rectifier (SCR) formed in a substrate and configured to transfer charge from a protected node to a negative power supply, V, during an ESD event, and a trigger device to activate transfer of charge by the SCR when a voltage on the protected node reaches a predetermined trigger voltage. The trigger device includes a gated-diode and MOS capacitor formed in a well formed in the substrate, the trigger device configured to inject electrons into the well during charging of the MOS capacitor, forward biasing a node of the SCR, hence allowing fast triggering of the SCR device. The trigger voltage can be set independent of a holding voltage by adjusting the length of the well and area of the capacitor. Other embodiments are also disclosed.