The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 06, 2012

Filed:

Aug. 12, 2002
Applicants:

Michael J. Haji-sheikh, Dekalb, IL (US);

James R. Biard, Richardson, TX (US);

James K. Guenter, Garland, TX (US);

Bobby M. Hawkins, Wylie, TX (US);

Inventors:

Michael J. Haji-Sheikh, Dekalb, IL (US);

James R. Biard, Richardson, TX (US);

James K. Guenter, Garland, TX (US);

Bobby M. Hawkins, Wylie, TX (US);

Assignee:

Finisar Corporation, Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2006.01);
U.S. Cl.
CPC ...
Abstract

Disclosed are methods for providing wafer parasitic current control to a semiconductor wafer () having a substrate (), at least one active layer () and a surface layer (), and electrical contacts () formed on said surface layer (). Current control can be achieved with the formation of trenches () around electrical contacts, where electrical contacts and associated layers define an electronic device. Insulating implants () can be placed into trenches () and/or sacrificial layers () can be formed between electronic contacts (). Trenches control current by promoting current flow within active (e.g., conductive) regions () and impeding current flow through inactive (e.g., nonconductive) regions (). Methods of and systems for wafer level burn-in (WLBI) of semiconductor devices are also disclosed. Current control at the wafer level is important when using WLBI methods and systems.


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