The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 28, 2012
Filed:
Nov. 02, 2007
Michael C. Shebanow, Saratoga, CA (US);
John S. Montrym, Los Altos Hills, CA (US);
Richard A. Silkebakken, Santa Clara, CA (US);
Robert C. Keller, Palo Alto, CA (US);
Michael C. Shebanow, Saratoga, CA (US);
John S. Montrym, Los Altos Hills, CA (US);
Richard A. Silkebakken, Santa Clara, CA (US);
Robert C. Keller, Palo Alto, CA (US);
NVIDIA Corporation, Santa Clara, CA (US);
Abstract
Processing units are configured to capture the unit state in unit level error status registers when a runtime error event is detected in order to facilitate debugging of runtime errors. The reporting of warnings may be disabled or enabled to selectively monitor each processing unit. Warnings for each processing unit are propagated to an exception register in a front end monitoring unit. The warnings are then aggregated and propagated to an interrupt register in a front end monitoring unit in order to selectively generate an interrupt and facilitate debugging. A debugging application may be used to query the interrupt, exception, and unit level error status registers to determine the cause of the error. A default error handling behavior that overrides error conditions may be used in conjunction with the hardware warning protocol to allow the processing units to continue operating and facilitate in the debug of runtime errors.