The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 28, 2012

Filed:

Aug. 04, 2004
Applicants:

Kazuhito Tanaka, Ohtsu, JP;

Akio Niwa, Takatsuki, JP;

Mitsuhiro Kasahara, Hirakata, JP;

Tadayuki Masumori, Osaka, JP;

Mamoru Seike, Takatsuki, JP;

Inventors:

Kazuhito Tanaka, Ohtsu, JP;

Akio Niwa, Takatsuki, JP;

Mitsuhiro Kasahara, Hirakata, JP;

Tadayuki Masumori, Osaka, JP;

Mamoru Seike, Takatsuki, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G 3/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

A test pattern generation circuit outputs a test pattern during a clock phase adjustment period. A flip-flop circuit latches the test pattern at the fall of a shift clock and outputs it as a test pattern. A latch miss detection circuit outputs a latch miss detection signal indicating presence/absence of a latch miss generation according to the test pattern and a delay shift clock. A clock phase controller delays the shift clock according to the latch miss detection signal, thereby outputting a delay shift clock.


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