The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 28, 2012
Filed:
Feb. 07, 2006
Mitsuhiko Sakai, Kyoto, JP;
Atsushi Yamaguchi, Kyoto, JP;
Ken Nakahara, Kyoto, JP;
Masayuki Sonobe, Kyoto, JP;
Tsuyoshi Tsutsui, Hyogo, JP;
Mitsuhiko Sakai, Kyoto, JP;
Atsushi Yamaguchi, Kyoto, JP;
Ken Nakahara, Kyoto, JP;
Masayuki Sonobe, Kyoto, JP;
Tsuyoshi Tsutsui, Hyogo, JP;
Rohm Co., Ltd., Kyoto, JP;
Abstract
There are provided a nitride semiconductor light emitting device having a structure enabling enhanced external quantum efficiency by effectively taking out light which is apt to repeat total reflection within a semiconductor lamination portion and a substrate and attenuate, and a method for manufacturing the same. A semiconductor lamination portion () including a first conductivity type layer and a second conductivity type layer, made of nitride semiconductor, is provided on a surface of the substrate () made of, for example, sapphire or the like. A first electrode (for example, p-side electrode ()) is provided electrically connected to the first conductivity type layer (for example, p-type layer ()) on a surface side of the semiconductor lamination portion (), and a second electrode (for example, n-side electrode ()) is provided electrically connected to the second conductivity type layer (for example, n-type layer ()). A part of the semiconductor lamination portion () is removed at a surrounding region of a chip of the semiconductor lamination portion () by etching so that column portions () stand side by side by leaving the semiconductor lamination portion without etching, and the n-type layer () expose around the column portions ().