The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 21, 2012
Filed:
Jul. 27, 2009
Vishwas M. Rao, Breinigsville, PA (US);
James C. Parker, Zionsville, PA (US);
Stephen A. Masnica, Macungie, PA (US);
Robert C. Sibert, Bethlehem, PA (US);
Vishwas M. Rao, Breinigsville, PA (US);
James C. Parker, Zionsville, PA (US);
Stephen A. Masnica, Macungie, PA (US);
Robert C. Sibert, Bethlehem, PA (US);
LSI Corporation, Milpitas, CA (US);
Abstract
Methods for establishing benchmarks and for analyzing benefits associated with voltage scaling are provided. In one embodiment, the method for establishing benchmarks includes: (1) synthesizing a netlist from a RTL of a functional IC design; (2) implementing a layout of an IC from the netlist, wherein the synthesizing and the implementing are performed at designated voltages and frequencies over a voltage and a frequency range, the voltage range including a voltage scaling range and a voltage associated with a designated implementation of the IC; (3) obtaining measurements of at least one voltage scaling metric associated with the IC at each of the designated voltages and frequencies; and (4) normalizing measurements associated with the voltage scaling range to measurements associated with the designated implementation employing a processor to obtain normalized benchmarks for analyzing optimization of the IC associated with voltage scaling. EDA tools may be used for synthesizing, implementing and obtaining.