The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 21, 2012
Filed:
Mar. 10, 2009
Ken Saito, Tokyo, JP;
Wataru Uchida, Tokyo, JP;
Ken Saito, Tokyo, JP;
Wataru Uchida, Tokyo, JP;
Renesas Electronics Corporation, Kanagawa, JP;
Abstract
An arrangement verification apparatus that makes it possible to shorten a time it takes to complete a failure/no-failure test on the arrangement of control circuits that control block circuits is provided. The arrangement verification apparatus arranges block circuits to be controlled comprising a semiconductor device and control circuits that control the block circuits over a predetermined floor and conducts a failure/no-failure test on the arrangement of the control circuits. The arrangement verification apparatus includes: a floor plan generation unit that arranges block circuits over a floor based on circuit specifications; a grouping generation unit that hierarchically groups the block circuits arranged over the floor and control circuits described in the circuit specifications based on a predetermined requirement to generate a group tree; a control circuit arrangement unit that arranges the control circuits over the floor according to a predetermined condition and the group tree generated at the grouping generation unit; and a failure/no-failure test unit that conducts a failure/no-failure test on the arrangement of the control circuits by the control circuit arrangement unit.