The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 21, 2012

Filed:

Nov. 05, 2008
Applicants:

Jack Dilullo, Austin, TX (US);

Ronald Nick Kalla, Round Rock, TX (US);

Gavin Balfour Meil, Round Rock, TX (US);

Jeffrey Mark Ritzinger, Chippewa Falls, WI (US);

Inventors:

Jack DiLullo, Austin, TX (US);

Ronald Nick Kalla, Round Rock, TX (US);

Gavin Balfour Meil, Round Rock, TX (US);

Jeffrey Mark Ritzinger, Chippewa Falls, WI (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/455 (2006.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

In accordance with an aspect of the present invention, specifying a portion of a circuit design to be treated as untimed by static timing analysis is performed on the RTL design by means of an attribute annotation. The process is operable to map through to the Physical Design by correlating latches and chip-level nets. This allows the testing process to become closed-loop. Design and simulation time is also greatly reduced due to the accessibility of RTL design.


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