Equivalence checking method, equivalence checking program, and generating method for equivalence checking program

Abstract

To provide a checking method that utilizes a test bench for a circuit model, which will serve as a fundamental for equivalence checking of a circuit to be newly developed for the fundamental circuit model. In order to check the equivalence of a model to be verified using a sample model a circuit of which has been described in a predetermined language and a test vector generation model for the sample model, a process for writing an output from the sample model test vector generation model into an input FIFO group for each signal of the sample model with the same timing as that of the sample model while the sample model is inputting/outputting a signal from/to the sample model test vector generation model with cycle accuracy and a process for reading data from the input FIFO group with the same operation timing as that of the model to be verified and outputting the data to the model to be verified are carried out. The output of the sample model and the output of the model to be verified are written into an output FIFO pair group for each corresponding signal name and coincidence judgment is carried out for a pair output for each written signal name.