The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 21, 2012

Filed:

Jun. 25, 2007
Applicants:

Chihtung Chen, San Diego, CA (US);

Inyup Kang, San Diego, CA (US);

Viraphol Chaiyakul, San Diego, CA (US);

Inventors:

Chihtung Chen, San Diego, CA (US);

Inyup Kang, San Diego, CA (US);

Viraphol Chaiyakul, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
Abstract

An N-dimension addressable memory. The memory includes an N-dimension array of bit cells and logic configured to address each bit cell using N-Dimension Addressing (NDA), where N is at least two and the array of bit cells is addressable by N orthogonal address spaces. Each bit cell of the N-dimension addressable memory includes a bit storage element, N word lines, and N bit lines.


Find Patent Forward Citations

Chen, Chihtung. (2012). Concurrent multiple-dimension word-addressable memory architecture (U.S. Patent No. 8120989). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8120989

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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