The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 21, 2012
Filed:
Feb. 12, 2010
William Robert Reohr, Ridgefield, CT (US);
John Edward Barth, Jr., Williston, VT (US);
Toshiaki Kirihata, Poughkeepsie, NY (US);
Derek H. Leu, Stormville, NY (US);
Donald W. Plass, Poughkeepsie, NY (US);
William Robert Reohr, Ridgefield, CT (US);
John Edward Barth, Jr., Williston, VT (US);
Toshiaki Kirihata, Poughkeepsie, NY (US);
Derek H. Leu, Stormville, NY (US);
Donald W. Plass, Poughkeepsie, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A word line driver circuit coupled to a memory circuit word line includes pull-up, pull-up clamp, pull-down and pull-down clamp transistors, each having a source, a drain and a gate. For the pull-up transistor, the source is coupled to a first power supply, and the gate to a pull-up control signal. For the pull-up clamp transistor, the source is coupled to the drain of the pull-up transistor, the drain to the word line, and the gate to a pull-up clamp gate signal. For the pull-down transistor, the source is coupled to a second power supply, and the gate to a pull-down control signal. For the pull-down clamp transistor, the source is coupled to the drain of the pull-down transistor, the drain to the word line, and the gate to a pull-down clamp gate signal. The word line is coupled to one or more DRAM cells. Source to drain voltage magnitudes of the pull-up and pull-down transistors are less than a voltage between the first and second power supplies.