Successive approximation analog/digital converter and time-interleaved successive approximation analog/digital converter

Abstract

A successive approximation analog/digital converter includes a sample & hold part sampling and holding an intensity of an analog input signal using a single clock cycle of a clock signal; a first comparator comparing the intensity of the analog input signal with comparison voltages determined according to estimated digital values per clock cycle following an operating clock cycle of the sample & hold part; a second comparator comparing the intensity of the analog input signal with a value equal to ½ of a preset reference voltage in the latter half of the operating clock cycle of the sample & hold part; a successive approximation register determining a value of an MSB of a digital value to be converted according to the comparison result of the second comparator and values of bits successive to the MSB according to the comparison result of the first comparator, and generating the estimated digital values by applying estimated values to undetermined bits; and a digital/analog converter generating the comparison voltages using the estimated digital values and the reference voltage.