The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 21, 2012
Filed:
Jun. 26, 2009
Jianlin Yu, Cupertino, CA (US);
Michael Frank, Sunnyvale, CA (US);
Erik P. Machnicki, San Jose, CA (US);
Jerrold V. Hauck, Windermere, FL (US);
Jean-didier Allegrucci, Sunnyvale, CA (US);
Santiago Fernandez-gomez, Sunnyvale, CA (US);
Jianlin Yu, Cupertino, CA (US);
Michael Frank, Sunnyvale, CA (US);
Erik P. Machnicki, San Jose, CA (US);
Jerrold V. Hauck, Windermere, FL (US);
Jean-Didier Allegrucci, Sunnyvale, CA (US);
Santiago Fernandez-Gomez, Sunnyvale, CA (US);
Apple Inc., Cupertino, CA (US);
Abstract
Methods for enabling a secure test mode, and integrated circuits (IC's) implementing the same are disclosed. An IC may include a secure functional unit that is protected from access from test access circuitry during normal operation. The secure functional unit may be rendered inaccessible the test access circuitry of the IC following a completion of a test that includes testing of the secure functional unit. An embodiment of an IC that includes circuitry to delay entry into a test mode while a chip-level reset is performed is also contemplated. Entry into the test mode may be delayed until all circuitry of the IC has been fully reset in order to clear stored information.