The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 21, 2012
Filed:
Sep. 28, 2007
Jitesh Shah, Fremont, CA (US);
Jitesh Shah, Fremont, CA (US);
Integrated Device Technology, Inc., San Jose, CA (US);
Abstract
A package () for electrically connecting an integrated circuit () to a printed circuit board () includes a mount array () and a substrate body (A). The mount array () is electrically connected to the integrated circuit (). The mount array () includes a plurality of positive terminal mounts (), a plurality of negative terminal mounts (), and a plurality of signal mounts (). The substrate body (A) includes a first conductive layer (), a second conductive layer (), and an insulating layer () that is positioned between the first conductive layer () and the second conductive layer (). The first conductive layer () includes (i) a terminal portion () that is connected one of the terminal mounts () (), and (ii) a signal portion () that is connected to the signal mounts (). Further, the second conductive layer () is directly connected to the other of the terminal mounts () (). Additionally, the package () can include a capacitor () having a positive capacitor pad () and a negative capacitor pad (). The electrical path of the capacitor () to the mount array () in the designs provided herein is relatively short, has relatively low impedance, and has a relatively low loop inductance.