The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 21, 2012
Filed:
Apr. 01, 2010
Makoto Yoshida, Suwon-si, KR;
Hyeong-sun Hong, Seongnam-si, KR;
Kye-hee Yeom, Suwon-si, KR;
Dae-ik Kim, Yongin-si, KR;
Yong-il Kim, Hwaseong-si, KR;
Makoto Yoshida, Suwon-si, KR;
Hyeong-Sun Hong, Seongnam-si, KR;
Kye-Hee Yeom, Suwon-si, KR;
Dae-Ik Kim, Yongin-si, KR;
Yong-Il Kim, Hwaseong-si, KR;
Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;
Abstract
A semiconductor device, and a method of forming the same, includes forming a cell bit line pattern and a peripheral gate pattern on a semiconductor substrate. The cell bit line pattern may be formed on an inactive region adjacent to a cell active region of the semiconductor substrate. The peripheral gate pattern may be disposed on a peripheral active region of the semiconductor substrate. A cell contact plug may be formed between the cell bit line pattern and the cell active region. A peripheral contact plug may be formed on the peripheral active region on a side of the peripheral gate pattern. An insulating layer may be formed to expose top surfaces of the cell bit line pattern, the peripheral gate pattern, and the cell and peripheral contact plugs at substantially the same level.