The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8119512 B1

PDF
Full Text
Expired
Date of Patent:
Feb. 21, 2012

Filed:

Dec. 29, 2010
Applicant:

Chang-goo Lee, Gyeonggi-do, KR;

Inventor:

Chang-Goo Lee, Gyeonggi-do, KR;

Assignee:

Hynix Semiconductor Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for fabricating a semiconductor device includes forming an interlayer dielectric layer over a substrate; forming a dual storage node contact plug to be buried in the interlayer dielectric layer, forming a first damascene pattern to isolate the dual storage node contact plug, forming a protective layer pattern inside the first damascene pattern, etching the interlayer dielectric layer to form a second damascene pattern to be coupled to the first damascene pattern, and forming bit lines inside the first and second damascene patterns.


Find Patent Forward Citations

Lee, Chang-Goo. (2012). Method for fabricating semiconductor device with damascene bit line (U.S. Patent No. 8119512). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8119512

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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