The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 14, 2012
Filed:
Jan. 28, 2009
Vasisht M. Vadi, San Jose, CA (US);
Alvin Y. Ching, Sunnyvale, CA (US);
Subodh Kumar, San Jose, CA (US);
Richard D. Freeman, Soquel, CA (US);
Ian L. Mcewen, Golden, CO (US);
Philip R. Haratsaris, Longmont, CO (US);
Jaime D. Lujan, Louisville, CO (US);
Eric M. Schwarz, Boulder, CO (US);
Vasisht M. Vadi, San Jose, CA (US);
Alvin Y. Ching, Sunnyvale, CA (US);
Subodh Kumar, San Jose, CA (US);
Richard D. Freeman, Soquel, CA (US);
Ian L. McEwen, Golden, CO (US);
Philip R. Haratsaris, Longmont, CO (US);
Jaime D. Lujan, Louisville, CO (US);
Eric M. Schwarz, Boulder, CO (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A computer-implemented method of identifying timing paths of a circuit block can include representing a circuit block including at least one bypassable component as a block diagram having a plurality of elements linked by nodes. The method can include generating a map file including a text description of each element within the block diagram, wherein the text description of each element specifies a bypass indicator for the element. The method also can include generating a plurality of sub-paths from the map file, determining timing paths from the plurality of sub-paths by selectively combining different ones of the plurality of sub-paths according to commonality of starting points and ending points of the plurality of sub-paths, and outputting the timing paths.