The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 14, 2012

Filed:

Aug. 11, 2009
Applicants:

Toshinobu Nagasawa, Osaka, JP;

Tetsushi Toyooka, Kyoto, JP;

Masaharu Sato, Shiga, JP;

Inventors:

Toshinobu Nagasawa, Osaka, JP;

Tetsushi Toyooka, Kyoto, JP;

Masaharu Sato, Shiga, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02H 9/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

To provide a semiconductor integrated circuit including: a detection circuit that detects an occurrence of latch up and can be configured while adopting a layout configuration that suppresses the occurrence of latch up; and a recovery unit that enables a recovery from the latch up without cutting off a positive potential. The semiconductor integrated circuit includes: a n-channel MOS transistorthat is formed on a P-type regionon a semiconductor substrate; and a latch up detection circuit that detects an occurrence of latch up in the n-channel MOS transistor. The latch up detection circuit includes: a n-MOS transistor structurein which a sourceand a back gateare connected in common with a sourceand the back gateof the n-channel MOS transistor; and an electric current detection unitthat detects an electric current flowing to a drainof the n-MOS transistor structure


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