The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 14, 2012

Filed:

Dec. 17, 2009
Applicants:

Jea Gu Lee, Gumi-si, KR;

Seung Chul Kang, Gumi-si, KR;

Inventors:

Jea Gu Lee, Gumi-si, KR;

Seung Chul Kang, Gumi-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
Abstract

Provided is an electrophoretic display device and a method of manufacturing and repairing the electrophoretic display device. The electrophoretic display device includes: a gate line, a gate electrode, and a common electrode, separated a predetermined distance from the gate line, which are formed on a substrate; a gate insulation layer formed on an overall surface of the substrate including the gate line; a data line configured to define a pixel area by crossing the gate line; a source electrode configured to extend from the data line; a drain electrode separated from a predetermined distance from the source electrode; a protection layer formed on an overall surface of the substrate including the data line, the source electrode, and the drain electrode; a pixel electrode formed on the protection layer and connected to the drain electrode; an electrophoretic film formed on the substrate including the pixel electrode; a common line formed on a boundary portion between the pixel areas and configured to connect the common electrodes formed in the respective pixel areas; and a repair hole formed by removing the protection layer corresponding to the common line to expose the gate insulation layer.


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