The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8114747 B1

PDF
Full Text
Expired
Date of Patent:
Feb. 14, 2012

Filed:

Nov. 10, 2010
Applicants:

Phil Christopher Felice Paone, Rochester, MN (US);

David P. Paulsen, Dodge Center, MN (US);

John E. Sheets, Ii, Zumbrota, MN (US);

Kelly L. Williams, Rochester, MN (US);

Inventors:

Phil Christopher Felice Paone, Rochester, MN (US);

David P. Paulsen, Dodge Center, MN (US);

John E. Sheets, II, Zumbrota, MN (US);

Kelly L. Williams, Rochester, MN (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

A 3-D (Three Dimensional) inverter having a single gate electrode. The single gate electrode has a first gate dielectric between the gate electrode and a body of a first FET (Field Effect transistor) of a first doping type, the first FET having first source/drain regions in a semiconductor substrate, or in a well in the semiconductor substrate. The single gate electrode has a second gate dielectric between the gate electrode and a body of a second FET of opposite doping to the first FET. Second source/drain regions of the second FET are formed from epitaxial layers grown over the first source/drain regions.


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Paone, Phil Christopher Felice. (2012). Method for creating 3-d single gate inverter (U.S. Patent No. 8114747). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8114747

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