The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 14, 2012

Filed:

Oct. 08, 2007
Applicants:

Lee H. Tullidge, Urbana, OH (US);

Leonard DE Oto, Springfield, OH (US);

Tim Larson, Minnetonka, MN (US);

Patrick O'keefe, Minnetonka, MN (US);

Herb Gertz, Minnetonka, MN (US);

Inventors:

Lee H. Tullidge, Urbana, OH (US);

Leonard De Oto, Springfield, OH (US);

Tim Larson, Minnetonka, MN (US);

Patrick O'Keefe, Minnetonka, MN (US);

Herb Gertz, Minnetonka, MN (US);

Assignee:

Honeywell International Inc., Morristown, NJ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01K 3/10 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of heat sinking a surface mount device (SMD) component. In an example method through holes are formed in a printed circuit board (PCB), a first copper layer is electroless plated in the holes, a second copper layer is standard plated in the holes and surrounding surfaces of the PCB, a third copper layer is masked and pulse plated in the holes, the holes are filled with non-conductive material and then is sanded flush with the second copper layer. A fourth copper layer electroless plated on the PCB over the area of the holes, a fifth copper layer (or pad) plated on the PCB over the area of the holes, and a surface mount device is attached to the fifth copper layer.


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