Presetable ram

Abstract

A programmable volatile memory cell has a reset device in communication with a bit store. The reset device may produce a high or low logic state within a latch loop when activated by an assertive logic level on a reset line. A set of mask programmable vias may be provided on a single mask layer in a semiconductor fabrication process for the memory cell. A program-selectable one of two sets of vias may communicate with one reset device to the reset line and the other reset device to ground. In this way a single and programmatically determinable logic state may be produced in the memory cell with reset signaling. Otherwise, the memory cell is capable of retaining a logic state according to read/write processes. The memory cell may be implemented in an array where all or some of the cells may be reset at once.