Level shifter with balanced duty cycle

Abstract

A level shifter and method are provided for balancing a duty cycle of a signal. An input circuit receives a differential logic signal with two complimentary logic levels. A level transition balancing circuit balances the rise and fall times of a level shifted version of each complimentary logic level during a transition from a first to a second of the logic levels and a level shift. A logic element stores and provides outputs of the level shifted versions of the logic levels. The level transition balancing circuit can include a capacitor in parallel with a transfer element for each input. The capacitor destabilizes inputs to the logic element and balances the transition using a capacitance and a level previously stored in the logic element.