The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8111061 B1

PDF
Full Text
Expired
Date of Patent:
Feb. 07, 2012

Filed:

Jun. 09, 2009
Applicants:

Kouji Suzuki, Shioya, JP;

Kenichi Takebayashi, Shioya, JP;

Kazutaka Senoo, Shioya, JP;

Inventors:

Kouji Suzuki, Shioya, JP;

Kenichi Takebayashi, Shioya, JP;

Kazutaka Senoo, Shioya, JP;

Assignee:

Keihin Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 5/16 (2006.01); G01R 31/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

An embodiment of the present invention provides a multi-output determination circuit that determines whether or not any one input voltage of a plurality of input voltages is equal to or higher than an upper-limit voltage value. This multi-output determination circuit includes a first diode-OR, upper-limit reference voltage generation means, and a first comparator. The first diode-OR includes a plurality of first diodes whose anodes are each connected to a respective one of the plurality of input voltages and whose cathodes are connected in common. The upper-limit reference voltage generation means has a first resistor, the first diode, and a second resistor that are connected in series between first and second power supply potentials, and generates an upper-limit reference voltage based on the voltage of the cathode of the first diode. The first comparator compares the output voltage of the first diode-OR with the upper-limit reference voltage.


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