The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 2012

Filed:

Jul. 17, 2009
Applicants:

Douglas M. Dewanz, Rochester, MN (US);

Peter T. Freiburger, Rochester, MN (US);

David P. Paulsen, Dodge Center, MN (US);

John E. Sheets, Ii, Zumbrota, MN (US);

Inventors:

Douglas M. Dewanz, Rochester, MN (US);

Peter T. Freiburger, Rochester, MN (US);

David P. Paulsen, Dodge Center, MN (US);

John E. Sheets, II, Zumbrota, MN (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/04 (2006.01);
U.S. Cl.
CPC ...
Abstract

In a method of using a memory cell employing a field effect transistor (FET), the FET is heated to a first temperature sufficient to support bias temperature instability in the FET. The bit line is driven to a high voltage state. The word line is driven to a predetermined voltage state that causes bias temperature instability in the FET. The temperature, the high voltage state on the bit line and the predetermined voltage state on the word line are maintained for an amount of time sufficient to change a threshold voltage of the FET to a state where a desired data value is stored on the FET. The FET is cooled to a second temperature that is cooler than the first temperature after the amount of time has expired.


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