The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 2012

Filed:

Oct. 16, 2007
Applicants:

Teppei Iwase, Hyogo, JP;

Yoshihiro Tomura, Osaka, JP;

Kazuhiro Nobori, Osaka, JP;

Inventors:

Teppei Iwase, Hyogo, JP;

Yoshihiro Tomura, Osaka, JP;

Kazuhiro Nobori, Osaka, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
Abstract

In a semiconductor device mounted structure in which device electrodes of a semiconductor device and board electrodes of a board are connected to each other via bump electrodes, respectively, and in which a sealing-bonding resin is placed between the semiconductor device and the board, a void portion is placed at a position corresponding to an edge portion of the semiconductor device in the sealing-bonding resin. Thus, stress loads generated at corner portions of the semiconductor device due to board flexures for differences in thermal expansion and thermal contraction among the individual members caused by heating and cooling during mounting of the semiconductor device, as well as for mechanical loads after the mounting process, can be absorbed by the void portion and thereby reduced, so that breakdown of the semiconductor device mounted structure is prevented.


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