The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 2012

Filed:

Sep. 15, 2009
Applicant:

Kouji Tanaka, Kanagawa, JP;

Inventor:

Kouji Tanaka, Kanagawa, JP;

Assignee:

Renesas Electronics Corporation, Kawasaki-shi, Kanagawa, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/772 (2006.01); H01L 29/78 (2006.01); H01L 29/40 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
Abstract

Provided is a semiconductor device in which occurrence of humps can be suppressed and variations in characteristics of the semiconductor device can be suppressed. The semiconductor device includes: an element isolation film () formed in a semiconductor layer, the element isolation film () defining an element formation region; a gate electrode () formed above the element formation region, the gate electrode () having ends respectively extending above the element isolation film (); and impurity regions () which are to be a source region and a drain region which are formed in the element formation region so as to sandwich therebetween a channel formation region immediately under the gate electrode (), the gate electrode () including at each of the ends thereof a high work function region () in which work function is higher than work function in other regions over at least a part of an interface between the element formation region and the element isolation film ().


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