The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 24, 2012

Filed:

Mar. 09, 2007
Applicants:

Soumya Banerjee, San Jose, CA (US);

Todd Michael Bezenek, San Jose, CA (US);

Clement Tse, Fremont, CA (US);

Inventors:

Soumya Banerjee, San Jose, CA (US);

Todd Michael Bezenek, San Jose, CA (US);

Clement Tse, Fremont, CA (US);

Assignee:

MIPS Technologies, Inc., Sunnyvale, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A system and methods that facilitate the design process and minimize the time and effort required to complete the design and fabrication of an integrated circuits (IC) are described. The system and method utilize a plurality of repositories, rules engines and design and verification tools to analyze the workload and automatically produce a hardened GDSII description or other representation of the device. The system and method securely maintains synthesizable RTL on a server in a data center while providing designers access to portions of the mechanism by way of a network portal.


Find Patent Forward Citations

Banerjee, Soumya. (2012). System and method for managing the design and configuration of an integrated circuit semiconductor design (U.S. Patent No. 8103987). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8103987

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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