The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 24, 2012
Filed:
Apr. 19, 2004
Christopher J. Pettey, Cedar Park, TX (US);
Asif Khan, Cedar Park, TX (US);
Annette Pagan, Austin, TX (US);
Richard E. Pekkala, Austin, TX (US);
Robert Haskell Utley, Round Rock, TX (US);
Christopher J. Pettey, Cedar Park, TX (US);
Asif Khan, Cedar Park, TX (US);
Annette Pagan, Austin, TX (US);
Richard E. Pekkala, Austin, TX (US);
Robert Haskell Utley, Round Rock, TX (US);
Emulex Design and Manufacturing Corporation, Costa Mesa, CA (US);
Abstract
An apparatus and method are provided that enable I/O devices to be shared among multiple operating system domains. The apparatus has a first plurality of I/O ports, a second I/O port, and core logic. The first plurality of I/O ports is coupled to a plurality of operating system domains through a PCI Express fabric. Each of the first plurality of I/O ports is configured to route PCI Express transactions between said plurality of operating system domains and the switching apparatus. The second I/O port is coupled to a first shared input/output endpoint, where the first shared input/output endpoint is configured to request/complete said PCI Express transactions for each of the plurality of operating system domains. The core logic is coupled to the first plurality of I/O ports and the second I/O port. The core logic routes the PCI Express transactions between the first plurality of I/O ports and the second I/O port.