The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 24, 2012

Filed:

May. 22, 2007
Applicants:

Steffen Lehr, Villingen-Schwenningen, DE;

Patrick Vogel, Duesseldorf, DE;

Petrus Gijsbertus Maria Centen, Goirle, NL;

Jeoren Rotte, Breda, NL;

Ruud Van Ree, Breda, NL;

Heinrich Schemmann, Villigen-Schwenningen, DE;

Karl-heinz Schaaf, Villingen-Schwenningen, DE;

Sabine Roth, Moenchweiler, DE;

Inventors:

Steffen Lehr, Villingen-Schwenningen, DE;

Patrick Vogel, Duesseldorf, DE;

Petrus Gijsbertus Maria Centen, Goirle, NL;

Jeoren Rotte, Breda, NL;

Ruud van Ree, Breda, NL;

Heinrich Schemmann, Villigen-Schwenningen, DE;

Karl-Heinz Schaaf, Villingen-Schwenningen, DE;

Sabine Roth, Moenchweiler, DE;

Assignee:

Thomson Licensing, Boulogne, Billancourt, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 5/217 (2006.01); H04N 5/335 (2006.01); H03M 1/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

An image sensor circuit comprises a pixel cell array having a plurality of pixel cells arranged along a plurality of column lines, a plurality of readout circuits connected to said column lines, each of which comprises an analog-to-digital converter and a multiplexer for selectively applying an output signal of one of said column lines to said analog-to-digital converter. Between two of said column lines which are connected to a first one of said readout circuits located at a first side of said pixel cell array, there is a column line which is connected to a second one of said readout circuits located at a second side of said pixel cell array opposite to said first side.


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