The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 24, 2012
Filed:
Apr. 06, 2010
Carlos Velasquez, Neuchatel, CH;
Carlos Velasquez, Neuchatel, CH;
The Swatch Group Research and Development Ltd, Marin, CH;
Abstract
The amplifier circuit () includes a differential pair of PMOS transistors at input (P, P), whose source receives a current from a current source (). The gate of the first transistor (P) of the pair defines a non-inverting input (X) and the gate of the second transistor (P) of the pair defines an inverting input (X). A drain of the first transistor (P) of the differential pair is connected to a diode connected NMOS transistor (N) of a first current mirror (N, N), and a drain of the second transistor (P) of the differential pair is connected to a diode connected NMOS transistor (N) of a second current mirror (N, N). A diode connected PMOS transistor (P) of a third current mirror is connected to the drain of a second NMOS transistor (N) of the second current mirror, while a drain of a second PMOS transistor (P) of the third current mirror is connected to the drain of a second NMOS transistor (N) of the first current mirror to define a first output (OUT), which is inverted by a reverser (N, P) to supply an inverted output signal (OUT) capable of varying rail to rail. A first complementary NMOS transistor (N) is connected in the form of a reverser with the first PMOS transistor (P) of the differential pair. A second complementary NMOS transistor (N) is connected in the form of a reverser with the second MOS transistor (P) of the differential pair.