The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 24, 2012
Filed:
Apr. 14, 2010
Applicant:
Benyong Zhang, Auburn, WA (US);
Inventor:
Benyong Zhang, Auburn, WA (US);
Assignee:
National Semiconductor Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03L 7/06 (2006.01);
U.S. Cl.
CPC ...
Abstract
A clock signal generator and conditioner in which dual integrated phase-locked loop (PLL) circuits use an off-chip frequency-pullable crystal resonator or voltage-controlled oscillator (VCO) module and an on-chip VCO with intra-PLL frequency doubling to provide a clock signal with reduced in-band phase noise and RMS jitter. As desired, synchronization between the input and output clocks can also be provided.
Zhang, Benyong. (2012). Programmable dual phase-locked loop clock signal generator and conditioner (U.S. Patent No. 8102196). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8102196
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