The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 24, 2012

Filed:

Apr. 30, 2009
Applicants:

Anuj Batra, Dallas, TX (US);

Srinivas Lingam, Dallas, TX (US);

Kit Wing S. Lee, McKinney, TX (US);

Clive D. Bittlestone, Allen, TX (US);

Ekanayake A. Amerasekera, Dallas, TX (US);

Inventors:

Anuj Batra, Dallas, TX (US);

Srinivas Lingam, Dallas, TX (US);

Kit Wing S. Lee, McKinney, TX (US);

Clive D. Bittlestone, Allen, TX (US);

Ekanayake A. Amerasekera, Dallas, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 19/173 (2006.01);
U.S. Cl.
CPC ...
Abstract

An integrated circuit (IC) includes self-calibrating programmable digital logic circuitry. The IC includes at least one programmable digital logic cell, wherein the first programmable digital logic cell provides (i) a plurality of different accessible circuit configurations or (ii) a voltage level controller. A self-calibration system is provided that includes at least one reference device, a measurement device for measuring at least one electrical performance parameter that can affect a processing speed of the first programmable digital logic cell or at least one parameter that can affect the electrical performance parameter using the reference device to obtain calibration data. A processing device maps the calibration data or a parameter derived therefrom to generate a control signal that is operable to select from the plurality of different accessible circuit configurations or a voltage level output to change the processing speed of the programmable digital logic cell.


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