The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 17, 2012
Filed:
May. 28, 2010
Shih-chyn Lin, Hsin-Chu, TW;
Hsiang-pin Fan, Hsin-Chu, TW;
Wen-pin Chen, Hsin-Chu, TW;
Kuei-sheng Tseng, Hsin-Chu, TW;
Chen-yi Wu, Hsin-Chu, TW;
Shih-Chyn Lin, Hsin-Chu, TW;
Hsiang-Pin Fan, Hsin-Chu, TW;
Wen-Pin Chen, Hsin-Chu, TW;
Kuei-Sheng Tseng, Hsin-Chu, TW;
Chen-Yi Wu, Hsin-Chu, TW;
AU Optronics Corp., Hsin-Chu, TW;
Abstract
A shift register includes a control circuit, a pull-up circuit and a pull-down circuit. The control circuit generates a control signal according to a start pulse signal during being enabled. The pull-up circuit produces a gate pulse signal according to a clock signal during being enabled by the control signal. The pull-up circuit includes a dual-gate transistor. A first gate of the dual-gate transistor is electrically coupled to the control signal, a second gate of the dual-gate transistor is electrically coupled to a predetermined voltage, the source/drain of the dual-gate transistor serves as an output terminal for the gate pulse signal, and the drain/source of the dual-gate transistor is electrically coupled to the clock signal. The pull-down circuit pulls a potential at the first gate and another potential at the output terminal down to a power supply potential during the pull-up circuit is disabled.