The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 17, 2012

Filed:

May. 22, 2009
Applicants:

Farhad Fouladi, Los Altos Hills, CA (US);

Winnie W. Yeung, San Jose, CA (US);

Howard Cheng, Sammamish, WA (US);

Inventors:

Farhad Fouladi, Los Altos Hills, CA (US);

Winnie W. Yeung, San Jose, CA (US);

Howard Cheng, Sammamish, WA (US);

Assignee:

Nintendo Co., Ltd., Kyoto, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 5/36 (2006.01); G06F 13/18 (2006.01); G06F 13/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A graphics system including a custom graphics and audio processor produces exciting 2D and 3D graphics and surround sound. The system includes a graphics and audio processor including a 3D graphics pipeline and an audio digital signal processor. A memory controller performs a wide range of memory control related functions including arbitrating between various competing resources seeking access to main memory, handling memory latency and bandwidth requirements of the resources requesting memory access, buffering writes to reduce bus turn around, refreshing main memory, and protecting main memory using programmable registers. The memory controller minimizes memory read/write switching using a 'global' write queue which queues write requests from various diverse competing resources. In this fashion, multiple competing resources for memory writes are combined into one resource from which write requests are obtained. Memory coherency issues are addressed both within a single resource that has both read and write capabilities and among different resources by efficiently flushing write buffers associated with a resource.


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