The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 17, 2012
Filed:
Dec. 18, 2008
Hong-woo Lee, Cheonan-si, KR;
Jong-hwan Lee, Anyang-si, KR;
Beom-jun Kim, Seoul, KR;
Sung-man Kim, Seoul, KR;
Gyu-tae Kim, Cheonan-si, KR;
Kyoung-jun Jang, Asan-si, KR;
Hong-Woo Lee, Cheonan-si, KR;
Jong-Hwan Lee, Anyang-si, KR;
Beom-Jun Kim, Seoul, KR;
Sung-Man Kim, Seoul, KR;
Gyu-Tae Kim, Cheonan-si, KR;
Kyoung-Jun Jang, Asan-si, KR;
Abstract
A gate driving circuit includes cascaded stages, each including a pull-up part, a carry part, a pull-up driving part, a holding part and an inverter. The pull-up part pulls up a gate voltage to an input clock. The carry part pulls up a carry voltage to the input clock. The pull-up driving part is connected to a control terminal (Q-node) common to the carry part and the pull-up part, and receives a previous carry voltage from a previous stage to turn on the pull-up part and the carry part. The holding part holds the gate voltage at an off-voltage, and the inverter controls at least one of turning on the holding part and turning off the holding part based on an inverter clock. A high level of the inverter clock in a given horizontal period (1H) temporally precedes a high level of the input clock by a predetermined time interval.