The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 17, 2012

Filed:

Dec. 12, 2007
Applicant:

Hong-ro Lee, Suwon-si, KR;

Inventor:

Hong-Ro Lee, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/04 (2006.01); H01L 29/786 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
Abstract

A thin film transistor and a fabrication method thereof, in which one excimer laser annealing (ELA) makes a pixel portion and a driver portion different from each other in surface roughness and grain size. The thin film transistor includes: a substrate including a pixel portion and a driver portion; a first semiconductor layer disposed in the pixel portion and having a first surface roughness; a second semiconductor layer disposed in the driver portion and having a second surface roughness smaller than the first surface roughness; a gate insulating layer formed on the substrate including the first and second semiconductor layers; a first gate electrode placed to correspond to the first semiconductor layer on the gate insulating layer; a second gate electrode placed to correspond to the second semiconductor layer on the gate insulating layer; an interlayer insulating layer formed on the substrate including the first and second gate electrodes; first source and drain electrodes formed on the interlayer insulating layer and electrically connected with the first semiconductor layer; and second source and drain electrodes formed on the interlayer insulating layer and electrically connected with the second semiconductor layer.


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