Integrated circuit systems having processor-controlled clock signal generators therein that support efficient power management

Abstract

Exemplary embodiments of the invention provide a clock generation apparatus, system, and method, which include power management. The apparatus is couplable to second circuitry which has a clock input terminal and an inverted clock output terminal. An exemplary apparatus comprises a clock generator, a sensor, and a processor. The clock generator provides a clock signal on a first terminal which is couplable to the clock input terminal of the second circuitry. The sensor is coupled to a second terminal which is couplable to the inverted clock output terminal, and detects a power conservation mode and a power resumption mode of the second circuitry. The processor is adapted to reduce power to the clock generator and to provide a first predetermined voltage or a second predetermined voltage to the first and second terminals in response to the detection of the power conservation mode, and to increase power to the clock generator in response to the detection of the power resumption mode.