The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 10, 2012
Filed:
Sep. 04, 2008
Instruction fetch pipeline for superscalar digital signal processors and method of operation thereof
Vijayanand Angarai, Allen, TX (US);
Michelle Y. Che, Richardson, TX (US);
Asheesh Kashyap, Plano, TX (US);
Tracy Nguyen, The Colony, TX (US);
Vijayanand Angarai, Allen, TX (US);
Michelle Y. Che, Richardson, TX (US);
Asheesh Kashyap, Plano, TX (US);
Tracy Nguyen, The Colony, TX (US);
Verisilicon Holdings Co., Ltd., Santa Clara, CA (US);
Abstract
A next program counter (PC) value generator. The next PC value generator includes a discontinuity decoder that is provide to detect a discontinuity instruction among a plurality of instructions and a tight loop decoder that is provide to: a) detect a tight loop instruction, and b) provide a tight loop instruction target address. The next PC value generator further includes a next PC value logic having a plurality of inputs: a first input coupled to an output of the discontinuity decoder, and a second input coupled to an output of the tight loop decoder. The next PC value logic provides as an output, without a stall, a control signal that a next PC value is to be loaded with the tight loop instruction target address if: the discontinuity decoder detects a discontinuity instruction, and the tight loop decoder detects a tight loop instruction.