The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 10, 2012
Filed:
Aug. 19, 2008
Rotem Porat, Kfar Saba, IL;
Moshe Anschel, Kfar Saba, IL;
Itay Peled, Hod Hasharon, IL;
Erez Steinberg, Tel-Aviv, IL;
Ziv Zamsky, Raanana, IL;
Rotem Porat, Kfar Saba, IL;
Moshe Anschel, Kfar Saba, IL;
Itay Peled, Hod Hasharon, IL;
Erez Steinberg, Tel-Aviv, IL;
Ziv Zamsky, Raanana, IL;
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A method for address comparison, the method includes: (i) receiving an input address; (ii) determining whether the input address is within a memory segment out of a group of memory segments by comparing, in parallel, the input address to memory segment boundaries of each memory segment of the group; (iii) wherein a comparison between the input address and a memory segment boundary comprises: (a) applying a XOR operation on bits of a most significant portion of the input address and corresponding bits of a most significant portion of the memory segment boundary; (b) ignoring bits of a least significant portion of the input address and corresponding bits of a least significant portion of the memory segment boundary; and (c) comparing, by utilizing a set of full comparators, between bits of an intermediate portion of the input address and corresponding bits of an intermediate portion of the memory segment boundary; wherein a location of bits that form the intermediate portion of the input address and of the memory segment boundary is selected in response to an alignment restriction imposed on the memory segment, to a size of the memory segment and in response to a boundary restriction imposed on the memory segment.