The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 10, 2012

Filed:

Aug. 19, 2008
Applicants:

Deepak Mathew, Wilmington, MA (US);

Russ Mestechkin, Winchester, MA (US);

Prahallada Ponnathota, Woburn, MA (US);

Thomas F. Howe, Tyngsboro, MA (US);

Timothy Perrin Fisher-jeffes, Cambridge, MA (US);

Inventors:

Deepak Mathew, Wilmington, MA (US);

Russ Mestechkin, Winchester, MA (US);

Prahallada Ponnathota, Woburn, MA (US);

Thomas F. Howe, Tyngsboro, MA (US);

Timothy Perrin Fisher-Jeffes, Cambridge, MA (US);

Assignee:

MediaTek Inc., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 7/216 (2006.01);
U.S. Cl.
CPC ...
Abstract

A wireless device has a BRP-CRP interface that includes a dual-port frame memory having a first access port and a second access port in which data can be written to the dual-port frame memory through the first access port at the same time that data is read from the dual-port frame memory through the second access port. A bit rate processor performs bit rate processing on input data and writes data resulting from the bit rate processing to the dual-port frame memory through the first access port. A chip rate processor reads data from the dual-port frame memory through the second access port and performs chip rate processing on the data read from the dual-port frame memory. A data processor executes a software application that writes data to the dual-port frame memory through the first access port and reads data from the dual-port frame memory through the second access port.


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