The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 10, 2012

Filed:

Feb. 13, 2009
Applicants:

Nandakumar Krishnan, San Jose, CA (US);

Xinli Gu, San Jose, CA (US);

LI LI, San Jose, CA (US);

Jie Xue, San Jose, CA (US);

Jonathan M. Parlan, San Jose, CA (US);

Inventors:

Nandakumar Krishnan, San Jose, CA (US);

Xinli Gu, San Jose, CA (US);

Li Li, San Jose, CA (US);

Jie Xue, San Jose, CA (US);

Jonathan M. Parlan, San Jose, CA (US);

Assignee:

Cisco Technology, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/304 (2006.01); G01R 31/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

In one embodiment, the reliability of the L2 power and/or ground sub-arrays of contacts of a functional integrated circuit device is verified by applying a reference voltage to a selected contact in sub-array and sequentially measuring the voltage at other contacts in the sub-array. If the voltage levels are greater than a threshold voltage level then the functional integrated circuit device is verified as being reliable.


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